Univerance Labs

We’re
engineering
the
future The Univerance Labs UL monogram rendered in polished glass and gold from
Silicon
to
SaaS

Designing, developing, and commercializing technology for tomorrow

  • The Foundation

    EDA & Silicon Development

    GPU-native chip design, advanced verification, design-space optimization, foundry orchestration, and custom silicon validation

  • The Physical Layer

    Hardware & Edge Computing

    Translating our silicon expertise into purpose-built hardware, optimized edge devices, and embedded systems designed for high-performance computing

  • The Application Layer

    Digital Products & SaaS

    Developing scalable web and mobile applications, intelligent cloud platforms, and decision infrastructure that leverage our core compute technologies

  • The Scalability Engine

    IP Development & Licensing

    Packaging our advanced solvers, simulation models, and semiconductor logic into licensable IP for partners and future spin-off companies

Current Offering

ORAX Trust LC‑100

A fail‑closed hardware lifecycle controller for SkyWater SKY130A, delivered as both synthesizable soft IP and a hardened macro. Monotonic thermometer‑coded lifecycle transitions, authorization checks, OTP programming handshake control, debug policy enforcement, fault latching, and a saturating denied‑transition counter — every unknown or unauthorized state fails closed.

The ORAX Trust LC-100 shown as a packaged part in three-quarter view, its die surface rendered from the submitted GDSII, ringed by gold bond pads.
Die surface rendered from the submitted GDSII — 300 × 300 µm, 572,023 polygons across 11 mask layers on SKY130A. Package shown for illustration.
Process
SkyWater SKY130A · 130 nm
Integration
ChipIgnite Caravel user‑project wrapper
Gate count
1,962
Target core clock
40 MHz
User‑project area
10.28 mm²
Timing corners
9 · ss/tt/ff, −40 °C to 100 °C, 1.60–1.95 V
Interface
Wishbone target, 5 registers, 29‑bit observation vector, 3 interrupts
Status
Submitted to ChipFoundry shuttle CI2609 — awaiting fabrication

  • Soft IP

    Synthesizable RTL

    SystemVerilog source, structural gate‑level netlists, and SDC timing constraints. Retarget to your process and integrate into your own SoC.

  • Hard IP

    Hardened Macro

    GDSII, LEF and Magic abstract views, Liberty timing models across all nine corners, DEF placement, and SPEF parasitics with an LVS configuration. Drop‑in for SKY130A.

Request the LC‑100 datasheet

Our Approach

We’re solving the hardest computational problems at the silicon level, then compounding that technology across hardware, software, and licensed IP

  1. Build highly optimized, compute-efficient foundations with Electronic Design Automation (EDA) and semiconductor design

  2. Leverage these core capabilities to develop our own advanced hardware, launch scalable SaaS applications

  3. License our proprietary IP to partners across industries. We build the hard tech once, and deploy it everywhere

Industries We Serve

Whether accelerating chip design, licensing IP,
or launching complex hardware and software,
Univerance Labs is your innovation engine

Connect with Us

Leadership